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Design of Cost-Efficient Interconnect Processing Units
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Design of Cost-Efficient Interconnect Processing Units : Spidergon STNoC

Book Details

Format Hardback or Cased Book
ISBN-10 1420044710
ISBN-13 9781420044713
Publisher Taylor & Francis Inc
Imprint CRC Press Inc
Country of Manufacture US
Country of Publication GB
Publication Date Sep 17th, 2008
Print length 288 Pages
Weight 657 grams
Ksh 26,300.00
Werezi Extended Catalogue 0 in stock

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Written by leading experts in the field, Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC comprehensively examines the current state-of-the-art and future trends in multiprocessor system-on-chip (MPSoC), in particular network-on-chip (NoC) design.

Streamlined Design Solutions Specifically for NoC
To solve critical network-on-chip (NoC) architecture and design problems related to structure, performance and modularity, engineers generally rely on guidance from the abundance of literature about better-understood system-level interconnection networks. However, on-chip networks present several distinct challenges that require novel and specialized solutions not found in the tried-and-true system-level techniques.

A Balanced Analysis of NoC Architecture
As the first detailed description of the commercial Spidergon STNoC architecture, Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC examines the highly regarded, cost-cutting technology that is set to replace well-known shared bus architectures, such as STBus, for demanding multiprocessor system-on-chip (SoC) applications. Employing a balanced, well-organized structure, simple teaching methods, numerous illustrations, and easy-to-understand examples, the authors explain:

  • how the SoC and NoC technology works
  • why developers designed it the way they did
  • the system-level design methodology and tools used to configure the Spidergon STNoC architecture
  • differences in cost structure between NoCs and system-level networks

From professionals in computer sciences, electrical engineering, and other related fields, to semiconductor vendors and investors ? all readers will appreciate the encyclopedic treatment of background NoC information ranging from CMPs to the basics of interconnection networks. The text introduces innovative system-level design methodology and tools for efficient design space exploration and topology selection. It also provides a wealth of key theoretical and practical MPSoC and NoC topics, such as technological deep sub-micron effects, homogeneous and heterogeneous processor architectures, multicore SoC, interconnect processing units, generic NoC components, and embeddings of common communication patterns.


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