High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip
Softcover reprint of the original 1st ed. 2018
Book Details
Format
Paperback / Softback
Book Series
Computer Architecture and Design Methodologies
ISBN-10
9811093210
ISBN-13
9789811093210
Edition
Softcover reprint of the original 1st ed. 2018
Publisher
Springer Verlag, Singapore
Imprint
Springer Verlag, Singapore
Country of Manufacture
GB
Country of Publication
GB
Publication Date
May 12th, 2018
Print length
197 Pages
Product Classification:
Circuits & componentsElectronics: circuits and componentsComputer hardware
Ksh 16,200.00
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This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors.
This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures.
Get High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip by at the best price and quality guaranteed only at Werezi Africa's largest book ecommerce store. The book was published by Springer Verlag, Singapore and it has pages.
