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Logic Synthesis and Verification Algorithms
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Logic Synthesis and Verification Algorithms

Softcover reprint of the original 1st ed. 1996

Book Details

Format Paperback / Softback
ISBN-10 1475770367
ISBN-13 9781475770360
Edition Softcover reprint of the original 1st ed. 1996
Publisher Springer-Verlag New York Inc.
Imprint Springer-Verlag New York Inc.
Country of Manufacture GB
Country of Publication GB
Publication Date Mar 18th, 2013
Print length 564 Pages
Ksh 13,500.00
Werezi Extended Catalogue 0 in stock

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Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits).
Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation for both professionals and students.
Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits). It combines and integrates modern developments in logic synthesis and formal verification with the more traditional matter of Switching and Finite Automata Theory. The book also provides background material on Boolean algebra and discrete mathematics.
A unique feature of this text is the large collection of solved problems.
Throughout the text the algorithms covered are the subject of one or more problems based on the use of available synthesis programs.

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