Materials, Processes, Integration and Reliability in Advanced Interconnects for Micro- And Nanoelectronics : Symposium Held April 10–12, 2007, San Francisco, California, U.S.A.

This book provides a forum to exchange advances in materials, processes, integration, and reliability in advanced interconnects and packaging. The book also addresses interconnects for emerging technologies, including 3D chip stacking and optical interconnects, as well as interconnects for optoelectronics, plastic electronics and molecular electronics.

In 2004, the microelectronics industry quietly ushered in the Nanoelectronics Era with the mass production of sub-100nm node devices. The current leading-edge semiconductor chips in mass production - the so-called 90nm node devices - have a transistor gate length of less than 50nm. This rapid technological advancement in the semiconductor industry has been made possible by innovations in materials employed in both transistor fabrication (front-end-of-the-line, FEOL) and interconnect fabrication (back-end-of-the-line, BEOL). The 90nm node BEOL features copper (Cu) interconnects and dielectric materials with a low-dielectric constant (k) of about 3.0. However, for the next generations of 65nm node and beyond, evolutionary and revolutionary innovations in BEOL materials and processes are needed to fuel the continued, healthy growth of the semiconductor. This book provides a forum to exchange advances in materials, processes, integration, and reliability in advanced interconnects and packaging. The book also addresses interconnects for emerging technologies, including 3D chip stacking and optical interconnects, as well as interconnects for optoelectronics, plastic electronics and molecular electronics.