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This book covers advances in Negative Bias Temperature Instability (NBTI) and will prove useful to researchers and professionals in the semiconductor devices areas. NBTI continues to remain as an important reliability issue for CMOS transistors and circuits. Development of NBTI resilient technology relies on utilizing suitable stress conditions, artifact free measurements and accurate physics-based models for the reliable determination of degradation at end-of-life, as well as understanding the process, material and device architectural impacts. This book discusses: Ultra-fast measurements and modelling of parametric drift due to NBTI in different transistor architectures: planar bulk and FDSOI p-MOSFETs, p-FinFETs and GAA-SNS p-FETs, with Silicon and Silicon Germanium channels. BTI Analysis Tool (BAT), a comprehensive physics-based framework, to model the measured time kinetics of parametric drift during and after DC and ACstress, at different stress and recovery biases and temperature, as well as pulse duty cycle and frequency. The Reaction Diffusion (RD) model is used for generated interface traps, Transient Trap Occupancy Model (TTOM) for charge occupancy of the generated interface traps and their contribution, Activated Barrier Double Well Thermionic (ABDWT) model for hole trapping in pre-existing bulk gate insulator traps, and Reaction Diffusion Drift (RDD) model for bulk trap generation in the BAT framework; NBTI parametric drift is due to uncorrelated contributions from the trap generation (interface, bulk) and trapping processes. Analysis and modelling of Nitrogen incorporation into the gate insulator, Germanium incorporation into the channel, and mechanical stress effects due to changes in the transistor layout or device dimensions; similarities and differences of (100) surface dominated planar and GAA MOSFETs and (110) sidewall dominated FinFETs are analysed.

1.Basic features, process dependence and variability of NBTI in p-MOSFETs

1.1.Introduction

1.2.Measurement of NBTI kinetics

1.2.1. Ultra-fast measure-stress-measure method

1.2.2. Time evolution of stress and recovery

1.2.3. Impact of measurement delay

1.2.4. Voltage and temperature dependence

1.2.5. Duty cycle and frequency dependence

1.2.6. Empirical estimation of end-of-life degradation

1.3.Overview of NBTI process dependence

1.3.1. Impact of SiGe channel

1.3.2. Impact of Nitrogen

1.3.3. Impact of gate stack thickness scaling

1.3.4. Impact of fin dimension scaling

1.3.5. Impact of layout

1.4.NBTI in small area devices

1.4.1. Stress and recovery kinetics

1.4.2. Distribution of degradation

1.4.3. Correlation of variability and variable NBTI

1.4.4. Random Telegraph Noise

1.5.Physical mechanism of NBTI - an overview

1.6.Summary

2.NBTI kinetics modeling framework

2.1.Introduction

2.2.Overview of NBTI modeling framework

2.3.Generation and passivation of interface traps

2.3.1. Double interface Reaction-Diffusion (RD) model

2.3.2. Physical mechanism of defect depassivation

2.3.3. A discussion on RD model parameters

2.3.4. DCIV measurement method

2.3.5. Prediction of DCIV data

2.3.6. Analysis of Ge% and N% impact

2.3.7. Comparison of continuum and stochastic frameworks

2.4.Occupancy of generated interface traps

2.4.1. Transient Trap Occupancy Model (TTOM)

2.4.2. Validation of TTOM framework

2.5.Hole trapping in pre-existing bulk traps

2.6.Validation of TTOM enabled RD and hole trapping

2.7.Time Dependent Defect Spectroscopy (TDDS) analysis

2.8.Generation of bulk traps

2.9.Validation of TTOM enabled RD and bulk trap generation

2.10.Summary

3.Modeling of NBTI kinetics in HKMG Si and Si-capped SiGe p-MOSFETs

3.1.Introduction

3.2.Description of process splits

3.3.Analysis of Gate First HKMG planar devices

3.3.1. DC stress and recovery kinetics

3.3.2. Impact of measurement delay

3.3.3. Nitrogen impact on NBTI parameters

3.3.4. AC stress kinetics

3.4. Analysis of mean stress-recovery kinetics from small area devices

3.5. Process dependence of model parameters

3.6. Estimation of end-of-life degradation

3.6.1. Calculation by empirical method

3.6.2. Calculation by physical model

3.6.3. Comparison of empirical and physical methods

3.7.Analysis of Si-capped SiGe planar devices

3.7.1. Stress and recovery kinetics

3.7.2. Voltage acceleration factor

3.7.3. Process dependence of model parameters

3.7.4. Estimation of end-of-life degradation

3.8.Summary

4.Modeling of NBTI kinetics in HKMG Si and SiGe FDSOI MOSFETs

4.1.Introduction

4.2.Description of process splits

4.3.Analysis of measured data

4.3.1. Time kinetics of stress and recovery

4.3.2. Impact of Ge% and N%

4.3.3. Impact of layout (STI to active spacing)

4.3.4. Process dependence of model parameters

4.4.Explanation of process dependence

4.4.1. Impact of Ge% and N%

4.4.2. Impact of layout effect

4.5. Estimation of end-of-life degradation

4.6. Summary

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Recent Advances in PMOS Negative Bias Temperature Instability : Characterization and Modeling of Device Architecture, Material and Process Impact

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