System Level Design from HW/SW to Memory for Embedded Systems : 5th IFIP TC 10 International Embedded Systems Symposium, IESS 2015, Foz do Iguacu, Brazil, November 3–6, 2015, Proceedings
Softcover Reprint of the Original 1st 2017 ed.
Book Details
Format
Paperback / Softback
ISBN-10
3030079171
ISBN-13
9783030079178
Edition
Softcover Reprint of the Original 1st 2017 ed.
Publisher
Springer Nature Switzerland AG
Imprint
Springer Nature Switzerland AG
Country of Manufacture
GB
Country of Publication
GB
Publication Date
Dec 11th, 2018
Print length
231 Pages
Ksh 8,100.00
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The papers present a broad discussion on the design, analysis and verification of embedded and cyber-physical systems including design methodologies, verification, performance analysis, and real-time systems design.
This book constitutes the refereed proceedings of the 5th IFIP TC 10 International Embedded Systems Symposium, IESS 2015, held in Foz do Iguaçu, Brazil, in November 2015. The 18 full revised papers presented were carefully reviewed and selected from 25 submissions. The papers present a broad discussion on the design, analysis and verification of embedded and cyber-physical systems including design methodologies, verification, performance analysis, and real-time systems design. They are organized in the following topical sections: cyber-physical systems, system-level design; multi/many-core system design; memory system design; and embedded HW/SW design and applications.
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