Book Details
Format
Paperback / Softback
ISBN-10
9811544077
ISBN-13
9789811544071
Edition
2020 ed.
Publisher
Springer Verlag, Singapore
Imprint
Springer Verlag, Singapore
Country of Manufacture
GB
Country of Publication
GB
Publication Date
Jun 11th, 2021
Print length
252 Pages
Weight
432 grams
Dimensions
15.60 x 23.30 x 1.80 cms
Product Classification:
Circuits & componentsAlgorithms & data structures
Ksh 12,600.00
Werezi Extended Catalogue
Delivery in 28 days
Delivery Location
Delivery fee: Select location
Delivery in 28 days
Secure
Quality
Fast
This book introduces the reader to FPGA based design for RTL synthesis. The book builds the story from basic fundamentals of FPGA based designs to advance RTL design and verification concepts using SystemVerilog.
This book introduces the reader to FPGA based design for RTL synthesis. It describes simple to complex RTL design scenarios using SystemVerilog. The book builds the story from basic fundamentals of FPGA based designs to advance RTL design and verification concepts using SystemVerilog. It provides practical information on the issues in the RTL design and verification and how to overcome these. It focuses on writing efficient RTL codes using SystemVerilog, covers design for the Xilinx FPGAs and also includes implementable code examples. The contents of this book cover improvement of design performance, assertion based verification, verification planning, and architecture and system testing using FPGAs. The book can be used for classroom teaching or as a supplement in lab work for undergraduate and graduate coursework as well as for professional development and training programs. It will also be of interest to researchers and professionals interested in the RTL design for FPGA and ASIC.
Get SystemVerilog for Hardware Description by at the best price and quality guaranteed only at Werezi Africa's largest book ecommerce store. The book was published by Springer Verlag, Singapore and it has pages.