Fault Tolerant Computer Architecture
by
Daniel Sorin
Book Details
Format
Paperback / softback
Book Series
Synthesis Lectures on Computer Architecture
ISBN-10
3031005953
ISBN-13
9783031005954
Publisher
Springer International Publishing AG
Imprint
Springer International Publishing AG
Country of Manufacture
GB
Country of Publication
GB
Publication Date
May 17th, 2009
Print length
103 Pages
Weight
230 grams
Dimensions
18.90 x 23.60 x 1.10 cms
KSh 5,050.00
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For many years, most computer architects have pursued one primary goal: performance. Table of Contents: Introduction / Error Detection / Error Recovery / Diagnosis / Self-Repair / The Future
For many years, most computer architects have pursued one primary goal: performance. Architects have translated the ever-increasing abundance of ever-faster transistors provided by Moore''s law into remarkable increases in performance. Recently, however, the bounty provided by Moore''s law has been accompanied by several challenges that have arisen as devices have become smaller, including a decrease in dependability due to physical faults. In this book, we focus on the dependability challenge and the fault tolerance solutions that architects are developing to overcome it. The two main purposes of this book are to explore the key ideas in fault-tolerant computer architecture and to present the current state-of-the-art - over approximately the past 10 years - in academia and industry. Table of Contents: Introduction / Error Detection / Error Recovery / Diagnosis / Self-Repair / The Future
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