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Nano Interconnects
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Nano Interconnects : Device Physics, Modeling and Simulation

Book Details

Format Hardback or Cased Book
ISBN-10 0367610485
ISBN-13 9780367610487
Publisher Taylor & Francis Ltd
Imprint CRC Press
Country of Manufacture GB
Country of Publication GB
Publication Date Dec 24th, 2021
Print length 216 Pages
Weight 498 grams
Dimensions 15.90 x 24.20 x 2.10 cms
Product Classification: Circuits & components
Ksh 25,200.00
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The comprehensive textbook provides the electrical and thermal circuit modelling of carbon allotropes in a simplified and detailed manner. It will as an ideal study material for senior undergraduate and graduate students in the field of electrical engineering, electronics and communications engineering.

This textbook comprehensively covers on-chip interconnect dimension and application of carbon nanomaterials for modeling VLSI interconnect and buffer circuits.

It provides analysis of ultra-low power high speed nano-interconnects based on different facets such as material modeling, circuit modeling and the adoption of repeater insertion strategies and measurement techniques. It covers important topics including on-chip interconnects, interconnect modeling, electrical impedance modeling of on-chip interconnects, modeling of repeater buffer and variability analysis. Pedagogical features including solved problems and unsolved exercises are interspersed throughout the text for better understanding.

Aimed at senior undergraduate and graduate students in the field of electrical engineering, electronics and communications engineering for courses on Advanced VLSI Interconnects/Advanced VLSI Design/VLSI Interconnects/VLSI Design Automation and Techniques, this book:

  • Provides comprehensive coverage of fundamental concepts related to nanotube transistors and interconnects.
  • Discusses properties and performance of practical nanotube devices and related applications.
  • Covers physical and electrical phenomena of carbon nanotubes, as well as applications enabled by this nanotechnology.
  • Discusses the structure, properties, and characteristics of graphene-based on-chip interconnect.
  • Examines interconnect power and interconnect delay issues arising due to downscaling of device size.

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