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ASIC Design and Synthesis
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ASIC Design and Synthesis : RTL Design Using Verilog

2021 ed.

Book Details

Format Paperback / Softback
ISBN-10 9813346442
ISBN-13 9789813346444
Edition 2021 ed.
Publisher Springer Verlag, Singapore
Imprint Springer Verlag, Singapore
Country of Manufacture GB
Country of Publication GB
Publication Date Jan 8th, 2022
Print length 330 Pages
Ksh 21,600.00
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This book describes simple to complex ASIC design practical scenarios using Verilog. It also covers architecture design strategies, multiple clock domain designs, low-power design techniques, DFT, pre-layout STA and the overall ASIC design flow with case studies.
This book describes simple to complex ASIC design practical scenarios using Verilog. It builds a story from the basic fundamentals of ASIC designs to advanced RTL design concepts using Verilog. Looking at current trends of miniaturization, the contents provide practical information on the issues in ASIC design and synthesis using Synopsys DC and their solution. The book explains how to write efficient RTL using Verilog and how to improve design performance. It also covers architecture design strategies, multiple clock domain designs, low-power design techniques, DFT, pre-layout STA and the overall ASIC design flow with case studies. The contents of this book will be useful to practicing hardware engineers, students, and hobbyists looking to learn about ASIC design and synthesis.


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